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SERIAL COMMUNICATION INTERFACE (SCI)
It is a universal asynchronous receiver transmitter (UART) serial communications interface with standard NRZ format (one start bit, eight or nine data bits, and one stop bit), which communicates with other device. For SCI several baud rates are available. The TXD and RXD pins are in port D, in which TXD is used for transmission and RXD is used for receiving operation. SIP is separated from SCI in 68HC11.
The functionality of SCI can be understood . The user has option bits in serial communications control register 1 (SCCR1) to determine the "wake-up" mode and data word length of the SCI. Serial communications control register 2 (SCCR2) provides control bits which individually enable/disable the transmitter or receiver (TE and RE, respectively), enable system interrupts (TIE, TCIE, ILIE) and provide the wake-up enable bit (RWU) and the send break code bit (SBK). The baud rate register (BAUD) bits allow the user to select different baud rates that may be used as the rate control for the transmitter and receiver.
Data transmission is initiated by a write to the serial communications data register (SCDR). Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data shift register. This transfer of data sets the TDRE bit of the SCI status register (SCSR) and generate an interrupt if the transmit interrupt is enabled. The transfer of data to the transmit data shift register is synchronized with the bit rate clock. All data is transmitted LSB first. Upon completion of data transmission, the transmission complete (TC) bit of the SCSR is set (provided no pending data, preamble, or break is to be sent), and an interrupt generated if the transmit complete interrupt is enabled. If the transmitter is disable and the data, preamble, or break (in the transmit shift register) has been sent, the TC bit will also be set. This will also generate an interrupt if the TCIE bit is set. If the transmitter is disabled in the middle of a transmission, that character will be completed before the transmitter gives up control of the TxD pin. When the SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The RDRF bit of the SCSR is set to indicate that a data byte has been transferred from the input serial shift register to the SCDR, which can cause an interrupt if the receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is synchronized by the receiver bit rate clock. The OR (over-run), NF (noise), or FE (framing) error bits of the SCSR may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects idle line transmission) of SCSR is set. This allows a receiver that is not in the wake-up mode to detect the end of a message, the preamble of a new message, or to resynchronize with the transmitter. A valid character must be received before the idle line condition or the IDLE bit will not be set and an idle line interrupt will not be generated.
SERIAL PEIRIPHERAL INTERFACE (SPI):
It is independent of SCI, allows the microcontroller to communicate synchronously with peripheral devices such as TTL shift register, LCD driver, A/D converter system and other microprocessor. The SPI is also capable of inter processor communication in a multiple master system. The SPI system can be configured as either a master or a slave device with data rates as high as 1/2 E clock rates when configured as master, and as fast as the E clock rate when configured as slave.
A SCK (serial clock) is generated by the master device and synchronizes data transmitted or received serially on master out slave in (MOSI) pins or master in slave out (MISO) pin. The SS (slave select) pin selects the slave device. In 8096 this corresponds to mode 0 of serial interface.
The functionality of SPI can be understood with the block diagram of the serial peripheral interface circuitry. When a master device transmits data to a slave device via the MOSI line, the slave device responds by sending data to the master device via the master's MISO line. This implies full duplex transmission with both data out and data in synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver7full status bits. A single status bit (SPIF) is used to signify that the I/O operation has been completed.
The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR is set.
DWOM
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR, until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of data and then SCK goes idle again.
In a slave mode, the slave start logic receives a logic low at the SS pin and a clock input at the SCK pin. Thus, the _lave is synchronized with the master. Data from the master is received serially at the slave MOSI line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave's MISO line.
Due to data direction register control of SPI outputs and the port D wire-OR mode (DWOM) option, the SPI system can be configured in a variety of ways. Systems with a single bidirectional data path rather than separate MISO and MOSI paths can be accommodated.
ANALOG TO DIGITAL CONVERTER
The A/D system is an 8-channel, 8-bit, multiplexed-input converter, successive approximation analog-to-digital (A/D) converter with sample and hold to minimize conversion errors caused by rapidly changing input signals accurate to 1 least significant bit (LSB) which includes = 1/ 2 LSB of quantization error.
It does not require external sample and hold circuit because of the type of charge redistribution technique used. A/D converter timing can be synchronized to the system E clock, or to an internal resister capacitor (RC) oscillator. The A/D converter system consists of four parts or functional blocks, multiplexer, analog converter, digital control and result storage. Its conversion time is 32 E clock if the E clock rate is greater than 750 kHz. For systems that operate at clock rates less than 750 kHz, an internal R-C oscillator must be used to clock the A/D system. E clock is an O/P corresponding to ¼ of oscillator frequency. This is same as 8096 A/D converter except A/D converter of 8096 is of 10 bits. The O/P of A/D converter is obtained on port E.
PROGRAMMABLE TIM.ER
TIMING SYSTEM
The M68HC11 timing is composed of five clock divider chain. The main clock divider chain includes a 16-bit free-running counter, which is driven by programmable prescaler. The programmable prescaler on the main timer provide one of the four clocking rates to derive the 16-bit counter. Two prescaler control bits select the prescaler rate.
The prescaler output dividing the system clock by 1,4,8 or 16. The clock circuitry generate the slower clock used by the pulse accumulator, the real time interrupt (RTI), and the computer operating properly (COP) watchdog subsystem.
WORKING OF TIMING SYSTEM
The 16-bit counter counts from $0000 to (as the microcontroller comes out of reset) and continues to max count, $FFFF. At max count, the counter rolls over to $0000, sets an overflow flag, and continues to increment. As long microcontroller running in normal operating mode, there is no way to reset, change, or interrupt the counting. The capture/compare subsystem features three I/P capture channels, four output compare channels, and one channel that can be selected to perform either input capture or output compare.
CONCLUSION
Advantages realized in implementing control applications on this family of microcontrollers are:
A more traditional architecture than other competing products (such as the 8051 and PIC) makes it easier to learn and develop on (especially well-suited for teaching
microcontrollers)
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More features
A 68HC11 is typically a "one-chip" solution since it often includes such items as A/D, PWM, and many I/O lines
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Popular
Widely used since it is very inexpensive and has a wide range of development tools available.
An overview of the M68HC11 family has been presented in this chapter. However for the interested readers programming aid is provided in Appendix E. The additional information on the M68HC11 can be refrenced from MOTOROLA "M68HC11 Refrence Manual".
UNSOLVED PROBLEMS
1. Describe Low Power Operation of 68HC11 microcontrollers.
2. Discuss the features of68HC11 series of micro controllers.
3. Write short notes on following 68HC11 microcontrollers features:
Serial Communications Interface
Serial Peripheral Interface
Low Power Modes
A to D Converter
4. Explain memory mapping of 68HC11 microcontrollers.
5. Write about Operating Modes of 68HC11 microcontrollers.
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