PROGRAM COUNTER (PC)
The program counter is a 16-bit register that contains the address of the next instruction to be executed.
CONDITION CODE REGISTER (CCR)
This 8-bit register contains five condition code indicators (C, V, Z, Hand N), two interrupt masking bit (IRQ and XIRQ) and a stop disable bit (S). Each bit of CCR signifies the results of the instruction just executed. The CCR have 8 bits
The function of each CCR bit is as follows:
CARRY/BORROW (C)
The C bit is set if there is a carry or borrow out of the arithmetic logic unit (ALU) after execution of last arithmetic operation. The C bit is also affected during shift and rotate instructions.
OVERFLOW (V)
The overflow bit is set if there is an arithmetic overflow as a result of the operation; otherwise, the V bit is cleared.
ZERO (Z)
The zero bit is set if the result after execution of arithmetic, logic, or data manipulation operation is zero; otherwise, the Z bit is cleared.
NEGATIVE (N)
The negative bit is set if the result of the last arithmetic, logic, or data manipulation operation is negative; otherwise, the N bit is cleared. A result is said to be negative if its most significant bit is a one.
INTERRUPT MASK (I)
The I interrupt mask bit is set either by hardware or program instruction to disable (mask), all maskable interrupt sources (both external and internal).
HALF CARRY (H)
The H bit is set when a carry occurs between bit-3 and 4 of the arithmetic logic unit during an ADD, ABA or ADC instruction. Otherwise, H bit is cleared; half carry is used during BCD operations.
X INTERRUPT MASK (X)
After any reset, X is set by default and must be cleared by software instruction. The X-interrupt mask bit is set only by hardware (RESET or XIRQ acknowledge), and it is cleared only by program instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value loaded into the CCR from the state has been cleared). There is no hardware action for clearing the X.
I/O PORTS
There are five I/O ports discussed as follows
Port A
In all operating modes, port A can be configured for four timer input capture (IC) functions and four timer output compare (OC) functions or for four OC and three IC function, and either a pulse accumulator input (PAD, or a fifth OC function.
Port B
During single chip-operation mode, all port B pins are general purpose O/P pins. Port B can also be used in a simple strobed output mode where an output pulse appeared at the STRB signal each time data is written to port B.
In expanded multiplexed operating mode, all port B pins act as high order address output signals (A8-A15). The Port B register is treated as an external address in expanded modes.
Port C
In single-chip operating mode, all port C pins are general purpose I/O pins. Port C can also be used in full handshake modes of parallel I/O where the STRA input and STRB output act as handshake control lines.
In expanded multiplexed modes, all port C pin act as multiplexed address/data signals. During the data portion of micro controller cycle these pins act as bidirectional data signal line. The direction of data at the port C pins is indicated by R/W signal.
Port D
Pins PD5-0 used as general purpose I/O signals. These pins alternatively serve as SCI (serial communication interface) and SPI (serial peripheral interface) signal when those subsystems are disabled.
Pin PD-O: Receive data input (RxD) signal for the SCL
Pin PDl: Transmit data output (TxD) signal for SCL
Pins PD5-2: Used for SPL
PD-2: Master in slave out (MISO) signal.
PD-3: Master out slave in (MOSD signal.
PD-4: Serial clock (SCK).
PD- 5: Slave select (SS) input.
Port E:
Use for general purpose or A/D Inputs. Reading port E should be avoided during sampling for high accuracy of AID conversion.
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