|
MEMORY
MAPPING
8048 series
Micro Computer separate memory in to two parts
-
Program
memory
-
Data
memory
PROGRAM
MEMORY
There
are three important locations in the program memory with addresses as 000H, 003H
and 007H. They are used as reset call subroutine, external interrupt call
subroutine external interrupt call subroutine and timer interrupt are subroutine
respectively. Therefore the first instruction to be executed after reset is
stored at location 000H, the external vector interrupt routine or a jump
instruction to a subroutine is stored as 003H and the first list of
counter/timer service routine is stored at 007H.
DATA
MEMORY
All 8048 series microcomputers provide 64 bytes of read/write memory on
chip. It is also called scratchpad memory or general purpose memory. There are
two register banks, each of eight bytes, known as RB0 and RB1 are located at location
00H to 07 H and 18 H to 1F H
respectively.
The
first two register of each set (R0 and Rl of RB0 and R01 and R11 of RB1) acts as
data counter to address the scratch pad memory and external data memory. For
this purpose implied addressing is used.
The data
memory has 16 reserved locations from 08H to 17H for stack levels designated as
S0 and S7 which are used during subroutine jump. The remaining data memory is
used for the general purpose.
In
addition, 256 bytes of external data memory can be addressed. The external data
memory space must be shared by scratchpad memory. The on chip scratchpad memory
has the addresses from 00 to 3F, where as the external data memory is addressed
from 00 to FF.
Instructions
that access scratchpad memory takes the scratchpad memory byte address from the
low order six bits of general purpose register R0 & R1.
Instructions
that access external data memory address from all eight bits of general purpose
register R0 & Rl.
INTERRUPTS (Internal and External Interrupts)
The 8048 series
microcomputer has a simple interrupt scheme that is effective and adequate for
small microcomputer. Interrupts can originate from 1 of 3 sources.
A RESET
This is a non-maskable
interrupt having highest priority and cannot be disabled.
AN EXTERNAL
INTERRUPT
It is induced by
setting INT. Low this is not available on the 8041 and 8021 series Micro
Computer
A COUNTER/TIMER
INTERRUPT
Their interrupt is
automatically requested every time the counter/time register increments from FFH
To 00H.
LOCATION AND
PRIORITY
When anyone of the
three interrupt requests is acknowledged the microcomputer executes a call
instruction to one of three locations.
When either an external interrupt or a counter/timer interrupt is
acknowledged, all interrupts (except Reset) are disabled until an RETR
instruction is executed. Within an External .. Timer interrupt service routine
user cannot enable interrupts under program control.
INSTRUCTION SET
'The MCS-48 instruction set is extensive for a machine of its size and
has been customized to be strightforward and very efficient in its use of
program memory. All instructions are either one or two bytes in length and over
80% are only one byte long.
The
MCS-48 microcomputers have been designed to handle arithmetic operations efficiently
in both binary and BCD as well as handle the single-bit operations required in
control applications. Special instructions have also been included to simplify
loop counters, table look-up routines, and N-way branch routines.
Data Transfers
The 8-bit accumulator is the central point for all data transfers within
the 8048. Data can be transferred between the 8 registers of each working
register bank and the accumulator directly i.e. . the source or destination
register is specified by the instruction. The remaining locations of the
internal RAM array are referred to as data memory and are addressed
indirectly via an address stored in
either R0 or R1 are of the active register bank. R0 and R1 are also used to
indirectly
address external data memory when it is present. Transfers to and from internal
RAM require one cycle, while transfers to external RAM require two. Constants
stored in program memory can be loaded directly to the accumulator and to the 8
working registers. Data can also be transferred directly between the accumulator
and the on-chip timer counter or the accumulator and the program status word (PSW).
Writing to the PSW alters machine status accordingly and provides a means of
restoring status after an interrupt or of altering the stack pointer if required.
Accumulator Operations
Immediate
data, data memory, or the working registers can be added with or without carry
to the accumulator. These sources can also be ANDed, ORed, or Exclusive ORed to
the accumulator. Data may be moved to or from the accumulator and working
registers or data memory. The two values can also be exchanged in a single
operation.
In
addition, the lower 4 bits of the accumulator can be exchanged with the lower
4-bits a[ any of the internal RAM locations. This instruction, along with an
instruction which swaps the upper and lower 4-bit halves of the of accumulator,
provides for easy handling of 4-bit quantities, including BCD numbers. For BCD
arithmetic, a Decimal Adjust instruction is included. This instruction is used
to correct the result of the binary addition of two 2-digit BCD numbers,
performing a decimal adjust on the result in the accumulator produces the
required BCD result.
Finally,
the accumulator can be incremented, decremented, cleared, or complemented and
can be rotated left or right 1 bit at a time with or without carry.
Although
there is no subtract instruction in the 8048AH this operation can be easily
implemented
with three single byte single-cycle instructions.
A value may be subtracted from the accumulator with the result in the
accumulator by
-
Complementing
the accumulator
-
Adding
the value to the accumulator
-
Complementing
the accumulator
Register operations
The working registers can be accessed via the accumulator as explained
earlier, or can be loaded immediate with constants from program memory. In
addition, they can be incremented or decremented or used as loop counters using
the decrement or used as loop counters using the decrement and jump, if not zero
instruction, explained under branch instructions.
All
data memory including working registers can be accessed with indirect
instructions via R0 and R1 and can be incremented.
Flags
There are four user-accessible flags in the 8048AH: Carry, Auxiliary
Carry, F0 and Fl. Carry indicates overflow of the accumulator, and auxiliary
carry is used to indicate overflow between BCD digits and is used during decimal
adjust operation. Both carry and auxiliary carry are accessible as part of the
program status word and are stored on the stack during subroutines. F0 and Fl
are undedicated general purpose flags to be ulsed by the programmer. Both
flags can be cleared or complemented and tested by conditional jump
instructions. F0 is also accessible via the program status word and is stored on
the stack with carry flags.
Branch Instructions
The unconditional jump instruction is two bytes and allows jumps
anywhere in the first 2K words of program memory. Jumps to the second 2K of
memory (4K words are directly addressable) are made first by executing a
select memory bank instruction, then executing the jump instruction. The 2K
boundary can only be crossed via a jump or subroutine call instruction, i.e., the
bank switch does not occur until a jump is executed. Once a memory bank has been
selected all subsequent jumps will be to the selected bank until another select
memory bank instruction is executed. A subroutine in the opposite bank can be
accessed by a select memory bank instruction followed by a call instruction.
Upon completion of subroutine, execution will automatically return to the
original bank; however, unless the original bank is reselected, the next jump
instruction encountered will again transfer execution to the opposite bank.
Conditional jumps can
test the following inputs and machine status
-
TO input pin
-
T1 input pin
-
INT input pin
-
Accumulator zero
-
Any bit of Accumulator
-
Carry Flag
-
F0 flags
- F1 flags
Conditional jumps allow a branch to any address within the current page
(256 words) of execution. The conditions tested are the instantaneous values at the time
the conditional jump is executed. For instance, the jump on accumulator zero
instruction tests the accumulator itself, not an intermediate zero flag.
A single-byte indirect jump instruction allows the program to be
vectored to anyone of several different location based on the vectored to
anyone of several different locations based on the contents of accumulator. The
contents of the accumulator points to a location in program
memory which
contains the jump address. The 8-bit jump address refers to the current page of
execution. This instruction could be used, for instance, to vector to anyone of several
routines based on an ASCII character which has been loaded in accumulator
.In this way ASCII key inputs can be
used to initiate various routines.
Subroutines
Subroutine
is entered by executing a call instruction. Calls can be made like unconditional
jumps to any address in a 2K word bank,
and jumps across the 2K boundary are executed in the same manner. Two
separate return instructions determine whether or not status (upper 4bits of
PSW)
is restored upon return from the subroutine.
The return and restore status instruction also signals the end of an
interrupt service routine if one has been in progress.
Timer Instructions
The 8 bit on board timer/counter can be loaded
or read via the accumulator while the counter is
stopped or while counting. The counter can be started as a timer
with an external clock applied to the T1 input pin. The
instruction executed determines which clock source is used. A signal instruction
stops the counter whether it is operating with an internal or an external clock source. In addition, two instructions allow the timer interrupt to be enabled or
disabled.
Control Instructions
There
are four memory bank select instructions, two to designate the active working
register bank and two to control program memory banks. The working
register bank switch instruction allow the programmer to immediately substitute a second
8-register working
register bank for the one in use. This effectively provides 16 working registers or it
can be used as a means of quickly saving the contents of the registers in response
to an interrupt. The user has the option to switch or not to switch banks on interrupt. However, if the banks are
switched, the original bank will be automatically restored upon execution of a
return and restore status instruction at the end of the interrupt service
routine.
A
special instruction enables an internal clock, which is the XTAL, frequency
divided by three to be output on pin T0. This clock can be used as a
general-purpose clock in the user's system.
Input/output Instruction
Ports 1 and 2 are 8-bit
static I/O ports can be accessed via the accumulator. Outputs are statically
latched but inputs are not latched and must be read while inputs are present.
An 8-bit port called the Bus can also be accessed via the accumulator
and can have statically latched outputs.
| Mnemonic |
Description |
Bytes |
Cycles |
| ADD A, R |
Add register to A |
1 |
1 |
| ADD A, @R |
Add data memory to R |
1 |
1 |
| ADD A, #data |
Add immediate to A |
2 |
2 |
| ADDC A, R |
Add register with carry |
1 |
1 |
| ADDC A, @ R |
Add data memory with carry |
1 |
1 |
| ADDC A, #data |
Add immediate with carry |
2 |
2 |
| ANL A, R |
AND register to A |
1 |
1 |
| ANL A, @R |
AND data memory to A |
1 |
1 |
| ANL A, #data |
AND immediate to A |
2 |
2 |
| ORL A, R |
OR register to A |
1 |
1 |
| ORL A, @R |
OR data memory to A |
1 |
1 |
| ORL A, #data |
OR immediate to A |
2 |
2 |
| XRL A, R |
Exclusive OR register to A |
1 |
1 |
| XRL A, @R |
Exclusive OR data memory to A |
1 |
1 |
| XRL A, #data |
Exclusive OR immediate to A |
2 |
2 |
| INCA |
Increment A |
1 |
1 |
| DECA |
Decrement A |
1 |
1 |
| CLRA |
Clear A |
1 |
1 |
| CPLA |
Complement A |
1 |
1 |
| DA A |
Decimal Adjust A |
1 |
1 |
| SWAP A |
Swap nibbles of A |
1 |
1 |
| RLA |
Rotate A left |
1 |
1 |
| RLCA |
Rotate A left through carry |
1 |
1 |
| RR A |
Rotate A right |
1 |
1 |
| RRCA |
Rotate A right through carry |
1 |
1 |
| Input/Output: |
|
|
|
| IN A,P |
Input port to A |
1 |
2 |
| OUTL P, A |
Output port to A |
1 |
2 |
| ANL P, #data |
AND-immediateto port |
2 |
2 |
| ORL P, #data |
OR immediate to port |
2 |
2 |
| *INS A, BUS |
Input BUS to A |
1 |
2 |
| *OUTL BUS, A |
Output A to BUS |
1 |
2 |
| *ANL BUS, #data |
AND immediate to BUS |
2 |
2 |
| *ORL BUS, #data |
OR immediate to BUS |
2 |
2 |
| MOYD A, P |
Input Expander port to A |
1 |
2 |
| MOVD P, A |
Output A to Expander port |
1 |
2 |
| M'LD P, A |
AND A to Expander port |
1 |
2 |
| ORLD P, A |
OR A to Expander port |
1 |
2 |
| Registers: |
|
|
|
| INC R |
Increment register |
1 |
1 |
| INC @R |
Increment data memory |
1 |
1 |
| DEC R |
Decrement register |
1 |
1 |
| Branch: |
|
|
|
| JMP addr |
Jump unconditional |
2 |
2 |
| JMPP @A |
Jump indirect |
1 |
2 |
| DJNZ R, addr |
Decrement register and jump |
2 |
2 |
| JC addr |
Jump if carrY = 1 |
2 |
2 |
| JNC addr |
Jump if carry = 0 |
2 |
2 |
| JZ addr |
Jump if A = 0 |
2 |
2 |
| JNZ addr |
Jump if A not zero |
2 |
2 |
| JT0 addr |
Jump if T0 = 1 |
2 |
2 |
| JNT0 addr |
Jump if T0 = 0 |
2 |
2 |
| JT1 addr |
Jump ifT1 =1I |
2 |
2 |
| JNT1 addr |
Jump ifT1 = 0 |
2 |
2 |
| JF0 addr |
Jump ifF0 = 1 |
2 |
2 |
| JF1 addr |
Jump ifF1 = 1 |
2 |
2 |
| JTF addr |
Jump if timer flag = 1 |
2 |
2 |
| JNI addr |
Jump if INT = 0 |
2 |
2 |
| JBb addr |
Jump on accumulator bit
' b' |
2 |
2 |
| Subroutine: |
|
|
|
| CALL addr |
Jump to subroutine |
2 |
2 |
| RET |
Return |
1 |
2 |
| RETR |
Return and restore status |
1 |
2 |
| Flags |
|
|
|
| CLR C |
Clear Carry |
1 |
1 |
| CPL C |
Complement Carry |
1 |
1 |
| CLR F0 |
Clear Flag 0 |
1 |
1 |
| CPL F0 |
Complement Flag 0 |
1 |
1 |
| CLR F1 |
Clear Flag 1 |
1 |
1 |
| CPL F1 |
Complement Flag 1 |
1 |
1 |
| Data Moves: |
|
|
|
| MOV A, R |
Move register to A |
1 |
1 |
| MOV A, @R |
Move data memory to A |
1 |
1 |
| MOV A, #data |
Move immediate to A |
2 |
2 |
| MOV R, A |
Move A to register |
1 |
1 |
| MOV @R, A |
Move A to data memory |
1 |
1 |
| MOV R, #data |
Move immediate to register |
2 |
2 |
| MOV @R, #data |
Move immediate to data memory |
2 |
2 |
| MOV A, PSW |
Move PSW to A |
1 |
1 |
| MOV PSW, A |
Move A to PSW |
1 |
1 |
| XCHA, R |
Exchange A and register |
1 |
1 |
| XCH A, @R |
Exchange A and data memory |
1 |
1 |
| XCHD A, @R |
Exchange nibble of A and register |
1 |
1 |
| MOVX A, @R |
Move external data memory to A |
1 |
2 |
| MOVX @R, A |
Move A to external data memory |
1 |
2 |
| MOVP A, @A |
Move to A from current page |
1 |
2 |
| MOVP3 A, @A |
Move to A from page 3 |
1 |
1 |
| Timer/Counter: |
|
|
|
| MOV A, T |
Read Timer/Counter |
1 |
1 |
| MOVT, A |
Load Timer/Counter |
1 |
1 |
| STRT T |
Start Timer |
1 |
1 |
| STRT CNT |
Start Counter |
1 |
1 |
| STOP TCNT |
Stop Timer/Counter |
1 |
1 |
| EN TCNTI |
Enable Timer/Counter Interrupt |
1 |
1 |
| DIS TCNTI |
Disable Timer/Counter Interrupt |
1 |
1 |
| Control: |
|
|
|
| EN I |
Enable external interrupt |
1 |
1 |
| DIS I |
Disable external interrupt |
1 |
1 |
| SEL RB0 |
Select register bank 0 |
1 |
1 |
| SEL RBI |
Select register bank 1 |
1 |
1 |
| SEL MB0 |
Select memory bank 0 |
1 |
1 |
| SEL MB1 |
Select memory bank 1 |
1 |
1 |
| ENTOCLK |
Enable clock output on T1 |
1 |
1 |
| NOP |
No operation |
1 |
1 |
|
