MEMORY MAP
Memory map for single-chip, expanded multiplexed, special bootstrap, and special test. Memory locations are the same for single-chip and expanded multiplexed modes.
The first 256 bytes from 0000 to 00FF constitute internal RAM. The 64 byte register block is mapped to $1000 after next and also corresponds to SFR of 8096. It can be placed at any other 4k boundry ($x000) by writing an value to the INIT register the 512 bytes of EEPROM be from B600H to B7FFH .The 8K internal ROM lies from F000H to FFFFH.
The special bootstrap operating mode memory locations are similar to the single-chip operating mode memory locations except that a bootstrap program at memory locations $BF40 through $BFFF is enabled. The reset and interrupt vectors are addressed at $BFC0-$BFFF while in the special bootstrap operating mode. These vector addresses are within the 192 byte memory used for the bootstrap program.
The special test operating mode memory map is the same as the expanded multiplexed operating mode memory map except that the reset and interrupt vectors are located at external memory locations $BFC0-$BFFF.
OPERATING MODES
For the MC6SHC11 there are four operating modes: single-chip operating mode, expanded multiplexed operating mode, special bootstrap operating mode, and special test operating mode.
The operating mode determined by the MODB and MODA mode select inputs during
reset.
Single-chip and expanded multiplexed are the normal mode. With Single-chip mode only on-board memory is available. Expanded multiplexed mode, however, allows access a external memory. Each of these modes is paired with a special mode .
Bootstrap, a variation of the single-chip mode that executes a boot loader program in an internal bootstrap ROM. Test, is a special mode that allows privileged access to internal resources.
SINGLE-CHIP OPERATING MODE
In this mode MC68HC11 has no external address or data bus. Port B, C, strobe A (STRA) and strobe B (STRB) are available for general purpose parallel I/O.
EXPANDED MULTIPLEXED OPERATING MODE
In this mode microcontroller can access a 64 Kbytes address space using multiplexed external address and data bus.
The expanded memory access is achieved by multiplexing the eight lower-order address lines with data on the port C pins. Only 18 pins are needed to provide an 8-bit data bus, a 16-bit address bus and two control lines. Port B is A [15:8], while port C is multiplexed AD [7:0). The address, R/W and AS signals are active and valid for all bus cycles.
SPECIAL TEST MODE
It is used during Motorola's internal production testing, however, it is accessible for programming the CONFIG register, programming calibration data into EEPROM, and debugging during development.
SPECIAL BOOTSTRAP MODE
When the micro controller is reset in the special bootstrap mode, a small on-chip ROM is enabled at address $BF40- $BFFF. This is a mask-programmed 192 byte ROM. The ROM contains a reset vector and a bootloader program. The microcontroller fetches the reset vector and then executes the bootloader.
INTERRUPTS
The micro controller has 18 interrupt vectors, in which 15 maskable interrupt vectors are generated by on-chip peripheral systems when global interrupt mask bit (I) in the condition code register (CCR) is clear. The 3 nonmaskable interrupt sources are illegal opcode trap. software interrupt, and XIRQ pin. The hardware interrupt corresponds to
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SCI serial system
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SPI serial transfer complete
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Pulse accumulator input edge
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Pulse accumulator overflow
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Timer overflow
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Timer input capture 4/output compare 5
- Real time interrupt
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Parallel I/O handshake
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IRQ (External pin)
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XIRQ pin
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Software interrupt (not hardware)
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Illegal opcode trap
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COP failure
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Clock monitor fail
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RESET
The software interrupt is executed in the same manner as any other instruction and will take precedence over interrupts only if the other interrupts are masked (I and X bit in the condition code register set).
LOW POWER OPERATION
In MC68HC11 there are two programmable low power modes:
STOP
Stop occurs when S bit (Stop disable) in the CCR (Condition code register) become zero. If the S bit is not zero (set), the stop opcode is treated as a no-operation (NOP) instruction. The stop condition offers minimum power consumption because all clocks, including the crystal oscillator, are stopped while in this mode. To exit STOP and resume normal processing, logic low level must be applied to one of the external interrupts (IRQ or XIRQ) or to the RESET pin. A pending edge-triggered IRQ can also bring the CPU out of STOP.
WAIT
The wait condition suspends processing and reduces power consumption to an intermediate level. During WAIT, the CPU register are stacked and CPU processing is suspended until a qualified interrupt is detected. The interrupt can be an external IRQ or XIRQ or internal interrupts such as the timer or serial interrupts. The on-chip crystal oscillator remain active throughout WAIT standby period.
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