• Oscillator
• State Counter
• Cycle Counter 

OSCILLATOR 
The on-board oscillator is a high gain parallel resonant circuit with a frequency range of 1 to 11 MHz. The X1 external pin is the input to the amplifier stage while X2 is the output. A crystal or ceramic resonator connected between X1 and X2 provides the feedback and phase shift required. 

(Ceramic resonator may be used in place of the crystal but for accurate clocking, a crystal should be used. An externally generated clock may also be applied to X1-X2 as the frequency source) 

STATE COUNTER 
The output of the oscillator is divided by 3 in the state counter to create a clock which defines the state times of the machine (CLK). CLK can be made available on the external pin T0 by executing an ENT0 CLK instruction. The output of CLK on T0 is disabled by Reset of the processor.

CYCLE COUNTER 
The output of the state counter CLK is then divided by 5 in the cycle counter to provide a clock which defines a machine cycle consisting of 5 machine states. This clock is called address latch enable (ALE) because of its function in MCS-48 system with external memory. It is provided continuously on the ALE output pin. 

8048 SERIES MICROCONTROLLER SIGNALS AND PIN DESCRIPTION 
 The processors of this series are packaged in 40 pin dual-in line-packaged.  

DB0-DB7 
It is a bi-directional I/O port, Data Bus and low-order address bus lines. It serves as a bi­directional I/O port, multiplexed data and address bus. This serves as a simple bi-directional I/O port or latch, when no external data or program memory accesses occur. This serves as a bi- directional data bus and lower memory address bus during external program or data memory accesses. These lines can write or read synchronously using RD and WR strobes. 

P10-P17 (Port 1) 
It is an 8 bit quasi-bi-directional port. 

P20-P27 (Port 2) 
It is also an 8-bit quasi-bi-directional port P20-P 23 are used to output the four high- order address of the program memory during external accesses. 

RD 
It is an output strobe, which is activated during a Bus read. This control signal is pulsed low to strobe data from external data memory onto the data bus. 

WR 
It is an output strobe which is activated during a BUS write. This control signal is strobe low when external data memory is to read data off the data bus i.e., when external memory is to be written by the data on the data bus. 

ALE 
ALE is an address latch enable which occurs once during each cycle and is used as an external clock signal. This control signal is pulsed high at the beginning of every instruction execution machine cycle. The trailing edge of ALE strobes the memory addresses being output during external memory accesses. 

 PSEN 
It is a program strobe enable signal used during the external program memory read. This control signal is strobe low when an external program memory is to place the data on to the data bus. 

 EA 
EA is an external access input which forces all program memory fetched to external memory. The External logic input this signal to high in order to separate the processor from interval program memory and forces the microcomputer in to debug mode. 

 SS 
It is a single step input which can be used in conjunction with ALE to single step the processor through each instruction. When it is put to low the instruction execution stops following an instruction fetch and allow the single step through a program. 

T0 
T0 is a bi-directional test input and is used while selecting external program mode and verifying mode it is used to output the internal CPU clock signal. . 

T1 
T1 is an input test input which can be sampled by a jump on instruction. It is used to input a signal to counter/timer logic when it is serving as an event counter. 

 XTALl, XTAL 2 
XTALI and XTAL2 are used for external crystal connections. XTAL1 is used to input a master clock signal for internal oscillator. The clock signal can be generated internally by connecting a crystal across XTAL1 or XTAL 2. 

PROG 
PROG is a program pulse used during the programming of EPROM of 8748 and 8749. These microcomputers use VDD and PROG in order to program the EPROM. For programming the EPROM a voltage of +25 V is input at V DD and +25 V pulse lasting 50 millisecond are input at PROG. During a signal pulse of PROG + 25 V, a single byte of program memory is written. 

Vcc 
Vcc is the standard main power supply, + 5V during operation. 

Vss 
Vss is the standard ground connection. 

VDD 
VDD is an additional + 5V stand by power supply to maintain the content of scratch pad memory when all other power is removed .It is connected to an external battery. It is also used as programming power supply. During programming of EPROM in case of 8748 and 8749 it is kept to + 25V. 

RESET 
 RESET is an input signal for system reset used to initialize the processor. There is an internal puIl-up resistor, which in combination with external 1uF capacitor generates internal RESET pulse. If the RESET pulse is generated externally, then it must be held low for at least 10ms.

SERIES TIMING AND INSTRUCTION EXECUTLON 
For 8048 series microcontrollers a master clock signal must be input via XTAL1, or the clock signal may be generated internally by connecting a crystal across XTAL1 or XTAL2. Generally a 6Mhz crystal is recommended. The clock signal is divided by 3 to generate a master' synchronizing 2MHz signal which is used throughout the microcomputers system. This 2 MHz clock signal can be output via the T0 pin. 

All eight versions of 8048 series microcomputers operate at half speed, they use 3 MHz crystals and generate a 1 MHz master-synchronizing signal. 

To execute an instruction-the processor must 

(1) Fetch the instruction from memory.
(2) Decode the instruction 
(3) Execute the instruction 
(4) Store the result back in the memory. These four steps refer to Instruction Cycle. 

Generally one machine cycle = X clock cycles ("X" depends on the particular instruction being executed). Shorter the clock cycle, lesser the time it takes to complete one machine cycle, so instructions are executed faster Hence, faster the processor. 

8048 machine cycle has five clock periods. Normally instructions executes in either one or two machine cycles. 

OPERATING MODES OF 8048 FAMILY 
8048 series microcomputer can operate in the following modes 

• Internal Execution Mode 
• External Memory Access Mode 
• Debug mode 
• Programming Mode 
• Verification Mode 

Depending upon the mode, many signals serves more than one function. 

  INTERNAL EXECUTION MODE
This series of microcomputer normally operates in this mode, when they execute programs without accessing the external program memory or data memory. All the transfer of information with external logic occurs through I/O port or control signals. The 8035 can't operate in this mode because it does not have internal program memory. 

One machine cycle contains five clock cycles. The instruction address is loaded before 1st clock cycle. During T1 the instruction is input while ALE is high. During T2 when ALE goes low the instruction is decoded and PC is incremented. During T3-T5, the instruction is executed and the next instruction address is output. 

EXTERNAL MEMORY ACCESS MODE 
8048 Microcomputer series have the capability of expandability and access external program and data memory for which the microcomputer outputs additional control signal, which identify the external program and data memory accesses. 

The memory addresses are output via the bus port and four pins of I/O port 2,the bi­directional data transfer via the bus port. The external memory address is via DBO-DB7 and P20-P23 and it is maintained stable for the time required for the external latch on the high-to-low transition of ALE. The PSEN serves as an external program memory read strobe. The external program memory must decode the latched address and place the contents of the addressed memory byte on DB0 when PSEN is low. 

In. the instruction fetch timing 'A' indicates address, I indicates instruction code an 'D' indicate I/O data. In case of Data Read /Write timings, A, DO and DI indicate address, data out and  data in respectively. The two machine cycle never occurs in a sequence, they have been just shown together for comparison purpose. 

In case of data read or write, RD is pulsed low to strobe data and WR is pulsed low to strobe data output. As the external memory address space is 256 bytes, the complete address is transmitted through DBO-DB7 and P20-P23 is in inactive during an excess of external data meemory. 

DEBUG MODE 
In this mode, the CPU is disconnected from its internal program memory and all program memory accesses are deflected to the external program memory. In case of 8035, it is always in debug mode because it has no internal program memory. Single stepping is the debugging adds in 8048 series microcomputers. 

In single-step, processor can be stepped through the program one instruction at a time. While stopped, the address of the next instruction to be fetched is available concurrently on BUS and lower half of Port 2. 

The CPU tests SS level only when ALE is high and at other times SS level is irrelevant. The current contents of program counter are output via Bus port DB0 -DB7 and P20-P23 when the microcomputer is stopped in a single step. 

 In any of the operating mode, one can apply a single step signal SS that halts the execution of instruction following the next instruction fetch. During this; one can execute the program by one instruction at a time in order to locate errors. 

PROGRAMMING MODE 
In this mode, one can program the EPROM contained in the microcomputers of this series. While programming and verifying the EPROM, one should input a clock signal of XTALl with a frequency between 1 MHz-6 MHz. For this purpose on-chip oscillator can also be used. The following steps are used to write or program the EPROM: 

• + 5V is applied at VDD. EA and RESET are held at ground. 
• To select the programming mode T0 is pulled to ground. 
• To activate the programming mode + 23 V is applied to EA. 
• To program 1024 bytes of program memory of 8748 device, l0-bit memory address is applied through DB0-DB7 and P20-P23. 
• RESET is given + 5 V to latch the address. 
• The data to be written is input on DB0-DB7. In order to write the data into the addressed program memory apply + 25 V to VDD and ground the PROG. Then apply +23 V pulse at PROG for at least 50 milliseconds. 
• The programming get completed on reducing V DD to + 5 V. 
• + 5 V is applied to T0 input to select the verify mode to verify the data just written. 

The EPROM has to be exposed to ultra-violet light for a minimum time of 20 minutes to erase its contents. 

VERIFY MODE 
In this mode one can read the contents of internal or external program memory as data. This mode is normally used in conjunction with the programming mode to test the data written into EPROM. However, it can also be used of its own to examine the contents of program memory for any of the microcomputers of this series. 

One can enter into verifying mode by applying +23V to EA pin and +5V to TO pin, the RESET pin has to held at ground. With 8048 series ROM, one can enter this mode by applying +12 V to the EA pin. The address of the program memory which is to be read is at DB0-DB7 and P20-P27 and is latched by applying + 5V to RESET. The contents of the addressed program memory are output via DB0-DB7, when RESET is high. The verification process can be repeated byte-by-byte. 

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