ARCHITECTURE
The 68HCll CPU has two 8 bit accumulators (A & B) that can be concatenated to provide a 16 bit double accumulator (D). Two 16 bit index registers (X, Y) are available to provide indexing to anywhere in the memory map. Having the two index registers means the 68HCll is very good for processing data. Although an eight bit processor, the 68HCll has some 16 bit instructions (add, subtract, 16 * 16 divide, 8 * 8 multiply, shift, and rotates). A 16 bit stack pointer is also present and instructions are provided for stack manipulation and multiplexed address and data bus.
The MC68HCll family have many versions but all are built around MC68HC11A8.
Onboard subsystems
TIMER
The 68HC11 timer system comprises of a single 16 bit counter, clocked at the E clock (2, 3, or 4 Mhz). There is a programmable prescaler to slow it down if required this single counter run a number of input capture and output compare registers (3-4 IC, 5-4 OC). The Input Capture and Output capture functions are very versatile, and pulses as short as 1 E clock can be generated.
A-D CONVERTER
The 68HC11 has typically 8 channel 8 bit A/D, although the G5 has a 10 bit A/D.
SERIAL COMMUNICATIONS INTERFACE (SCI)
Asynchronous serial communications; Data format-1 Start, 8 or 9 data, and one stop bit.
DATA RATE
The 68H11 data rate varies from 50 - 312500 Baud (312500 is using 4 mhz E clock).
SERIAL PERIPHERAL INTERFACE (SPI)
Synchronous serial communications comprises CLK, DATA IN, DATA OUT and optionally chip selects. As well as using specific SPI devices, it is very easy to expand IO using the SPI and standard logic devices (e.g. 74HC595 and 74HC165).
VnD and Vss
The microcontroller operates from a single 5-volt (nominal) power supply. V DD is the power supply and Vss is ground. Very fast signal transmission occur on the microcontroller pins. The short rise and fall times places high, short duration current demands on the power supply.
Functional Block Descriptions:
CENTRAL PROCESSING UNIT (CPU)
The 68HC11 CPU is designed to take care of all peripheral, I/O, and memory locations identically as addresses in the 64KB memory map. This is referred, as memory-mapped I/O. External memory can also be access with no execution-time delay.
CPU has two 8 bit accumulators (A & B) that can be concatenated to provide a 16 bit double accumulator (D). Two 16 bit index registers are present (X, Y) to provide indexing to anywhere in the memory map. A 16 bit stack pointer is also present and instructions are provided for stack manipulation.
CPU Registers:
M68HCll CPU registers are integral part of the CPU but cannot be addressed as memory locations. It has seven registers as shown in the Figure.
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ACCUMULATOR A |
ACCUMULATOR B |
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DOUBLE ACCUMULATOR D |
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INDEX REGISTER X |
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INDEX REGISTER Y |
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STACK POINTER |
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PROGRAM COUNTER |
ACCUMULATORS A, B AND D
Accumulators A, B are general purpose accumulator of 8 bit used for arithmetic calculation or data manipulation.
D is also accumulator (combination of A and B) but of 16 bit so called double accumulator.
INDEX REGISTER X (IX).
IX provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. The IX register can be used as a counter or as a temporary storage register.
INDEX REGISTER Y (IY) .
IY isl6-bit register same as IX but require an extra byte of machine code and an extra cycle of execution time because of the way the opcode map is implemented.
STACK POINTER (SP)
The stack pointer (SP) is a 16-bit register that contains the address of the next free location on the stack. The stack is configured as a sequence of LIFO read/write registers which allow data to be stored during interrupts and subroutine calls. Each time a new byte is added to the stack (a push instruction), the SP is decrement; whereas, each time a byte is removed from the stack (a pull instruction) the SP is incremented.
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