Intel introduced 8048 series of single chip microcomputer in 1976. Which become popular as MCS-48. Intel's MCS-48 system includes: 

The 8748, 8749, (EPROM devices)
The 8048, 8049, 8050 (ROM devices) and 
The 8035, 8039, 8040 CPU only devices. 
The 8049 are similar to 8048. The only difference is that 8049 has twice as much on chip ROM and its execution speed is 80% faster. 8035, 8039 & 8040 is similar to 8048 but have no on-chip program memory. 

8748 & 8749 have 1k and 2k bytes of EPROM respectively in place of ROM. So they requires an additional 25V supply for EPROM programming 

 The 8048 family have 8-bit CPU, 27 I/O lines, maximum 4k bytes of on-chip program, memory and 256 bytes of data memory and 256 bytes off chip RAM size. 

FUNCTIONAL OVERVIEW OF 8048/8049   
The functional block diagram of 8048 series microcontrollers has been shown in the following units 

• Arithmetic section 
• Memory section 
• Program Counter (12 bits) and Stack 
• I/O Ports (24 lines) 
• Program Status word (PSW) 
• Timer/ Counter (8 bits) 
• Clock & Timing Circuits 

Arithmetic Section 
It has four functional blocks for basic data manipulation: 

• Instruction decoder 
• Arithmetic Logic Unit (ALU) 
• Accumulator 
• Carry Flag 

The opcode portion of each instruction is stored in the instruction decoder and is converted in the signals (outputs to control the function of each block of arithmetic section. 

ALU perform all arithmetic and logic operation as per the signal generated by the instruction decoder. A carry flag is set in PSW in case of an overflow of MSB in the ALU operations. 

Accumulator is the most important data register in the microcomputer. This is one of the sources of the input to ALU and normally the destination of the result of operations performed in the ALU and. the processor communicate with the I/O and memory through accumulator. 

 Memory Section
8048 series microcomputer separate memory in to two parts 

• Program memory 
• Data memory 

Without expansion scheme maximum program memory and data memory is limited to 4096(4K) bytes and 320 bytes respectively. 

PROGRAM MEMORY 
Program memory consist of 1024 byte (lkb) in 8048 in the form of ROM each of 8 bit wide which can be address by a program counter of the Processor. In addition to this on-chip memory an additional memory can be interfaced to make 4 k Bytes. The total program memory is divided into memory bank 0 and memory bank 1. The bank 0 ranges from 000H to 7FFH is selected with the MSB of PC as Zero. The memory bank 1 range from 800H to FFFH is selected with MSB of PC as 1. 

DATA MEMORY 
8048 Micro---Computer has a resident data Memory of 64x8.bits (64 bytes). In addition, 256 bytes of external data memory may be addressed. 

Program Counter and Stack
In 8048 the program counter is an independent counter while the program counter stack is implemented using pairs of registers in the data array. The program counter is initialized to zero by activating the reset line.

An interrupt or CALL to a subroutine causes the contents of the PC to be stored in one of the 8-register pairs of the program counter stack. 

I/O Ports 
8048 Micro Controller has 24 I/O lines. These lines are grouped as three ports of eight lines. Three ports are port 1, port 2 and Bus port respectively. 

BUS PORT 
Bus port is used as primary I/O port in a single chip microcomputer system and serves as multiplexed address and data bus in a multiple-chip microcomputer system. 

It is a bi-directional I/O port with input and output strobes. Output can be statically latched, while inputs are non-latching. This means that external logic must hold input data true at Bus port pin until the data has been read, so one can't mix input and output on the Bus port. 

PORT 1 & 2 
The I/O port 1 and 2 are secondary I/O ports with different characteristics form the Bus port. 

Program Status Word 
In 8048 and 8 bits status word exists called the program status word (PSW). The PSW is actually a collection of flip-ftops throughout the machine which can be read or written as a whole. It can be loaded to and from the accumulator. The ability to write to PSW allows for easy restoration of machine status after a power down sequence.

The upper four bit of PSW are stored in the Program Counter Stack with every call to subroutine or interrupt vector and are optionally restored upon return with the RETR instruction. The RET return does not update PSW. 

The PSW bit definition is as follow. 
Bits 0-2      Stack pointer bits (S0, S1, S2) 
Bit 3           Not used ("1" level when read) 
Bit 4           Working Register Banks witch Bit (BS) 
                            0 = Bank 0 
                            1 = Bank1 
Bit 5      Flag 0 bit (F0) user controlled flag which can  be        completed or cleared and tested with the. conditional jump instruction JF0 

Bit 6 Auxiliary carry (AC) carry bit generated by an ADD instruction and used by the decimal adjust instruction DAA 

Bit 7 Carry (CY) carry flag which indicates that the previous operation has resulted in overflow of the accumulator 

Timer/Counter 
All 8048 series microcomputers have an internal counter/timer. Counter/timer logic may be illustrated. 

 The counter/timer register is 8 bits wide; it is accessed via an accumulator imstruction, which move accumulator contents to the counter/ timer register or more counter/timer register contents to the accumulator.

WORKING OF COUNTER/TlMER 

• Firstly, initial value are loaded into the timer/counter register. 
• Next start the counter/timer by executing the STRT T or STRT CNT instruction. (The counter/timer will increment continuously until stopped by a stop counter/timer instruction.). 
• When the .timer/counter increment from FFH to 00H, it activates a counter/timer interrupt request and sets a time-out flag. 

In case when the counter/timer interrupt has been enable, then program execution will branch to the corresponding interrupt service routine. If the counter! timer interrupt has been enabled then programmer must test for a time-out by executing the JT0 branch-on-condition instruction. 

• Counter/timer can be stopped by executing the STOP TCNT instruction. 

AS A TIMER 
The execution of STRT T instruction operates the counter/timer as a timer by connecting an internal clock to the counter input and enables the counter (Timer). The internal clock increments the counter every 32 m/c cycles. 

AS A COUNTER
 The execution of STRT CNT instruction operate the counter/timer as a counter by connecting the T1 input pin to the counter input and enables the counter. Now high to low transaction of a signal input at T1 increment the counter. The maximum rate at which the counter may be incremented is once per three instruction cycles, there is no minimum frequency. 


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